DS1977
PARAMETER
Presence Detect
Sample Time
SYMBOL
t MSP
CONDITIONS
Standard speed, V PUP > 4.5V
(Note 1)
Standard speed (Note 1)
MIN
65
68
TYP
MAX
75
75
UNITS
μs
I/O Pin, 1-Wire Write
Overdrive speed (Note 1)
7.5
10.5
Write-0 Low Time
Write-1 Low Time
t W0L
t W1L
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
60
6
5
1
120
16
15
2
μs
μs
I/O Pin, 1-Wire Read
Read Low Time
Read Sample Time
t RL
t MSR
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
Standard speed,
V PUP > 4.5V (Notes 1, 14)
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
5
1
t RL + δ
t RL + δ
t RL + δ
15 - δ
2- δ
20
15
2
μs
μs
I/O Pin, Strong Pullup
Strong Pullup Read
Strong Pullup Write
Strong Pullup password
verification
t SPUR
t SPUW
t SPUV
(Note 1)
(Note 1)
(Note 1)
2.64
22.46
0.62
ms
ms
ms
EEPROM
Programming Current
Write/Erase Cycles
Data Retention
I LPROG
N CYCLE
t RET
100k
10
7
mA
years
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the data pin could be 5nF when power is first applied.
V TL and V TH are functions of the internal supply voltage, which is a function of V PUP and the 1-Wire recovery times. The V TH and V TL
maximum specifications are valid at V PUPMAX (5.25V). In any case, V TL < V TH < V PUP .
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V ILMAX whenever the master drives the line low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V TH is crossed during a rising edge on I/O, the voltage on I/O has to drop by V HY to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t REH after V TH has been reached before.
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%
of V PUP and the time at which the voltage is 10% of V PUP .
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V IL to V TH . The actual maximum
duration for the master to pull the line low is t W1LMAX + t F - ε and t W0LMAX + t F - ε respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V IL to the input-high threshold of
the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + t F .
Parameter
Name
Standard Values
Standard Speed Overdrive Speed
min max min max
DS1977 Values
Standard Speed Overdrive Speed
min max min max
t SLOT (incl. t REC )
t RSTL
t PDH
t PDL
t W0L
61μs
480μs
15μs
60μs
60μs
(undef.)
(undef.)
60μs
240μs
120μs
7μs
48μs
2μs
8μs
6μs
(undef.)
80μs
6μs
24μs
16μs
65μs 1)
480μs
15μs
60μs
60μs
(undef.)
640μs
60μs
240μs
120μs
8μs 1)
48μs
2.5μs
8μs
6μs
(undef.)
80μs
6.5μs
24μs
16μs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
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